Verilog语言的循环语句示例详解

while (condition) begin
    …
end

`timescale 1ns/1ns
 
module test ;
 
    reg [3:0]    counter ;
    initial begin
        counter = 'b0 ;
        while (counter<=10) begin
            #10 ;
            counter = counter + 1'b1 ;
        end
    end
 
   //stop the simulation
    always begin
        #10 ;  if ($time >= 1000) $finish ;
    end
 
endmodule

for(initial_assignment; condition ; step_assignment)  begin
    …
end

// for 循环语句
integer      i ;
reg [3:0]    counter2 ;
initial begin
    counter2 = 'b0 ;
    for (i=0; i<=10; i=i+1) begin
        #10 ;
        counter2 = counter2 + 1'b1 ;
    end
end

repeat (loop_times) begin
    …
end

// repeat 循环语句
reg [3:0]    counter3 ;
initial begin
    counter3 = 'b0 ;
    repeat (11) begin  //重复11次
        #10 ;
        counter3 = counter3 + 1'b1 ;
    end
end

always @(posedge clk or negedge rstn) begin
    j = 0  ;
    if (!rstn) begin
        repeat (8) begin
            buffer[j]   <= 'b0 ;      //没有延迟的赋值，即同时赋值为0
            j = j + 1 ;
        end
    end
    else if (enable) begin
        repeat (8) begin
            @(posedge clk) buffer[j]    <= counter3 ;       //在下一个clk的上升沿赋值
            j = j + 1 ;
        end
     end
end

forever begin
    …
end

reg          clk ;
initial begin
    clk       = 0 ;
    forever begin
        clk = ~clk ;
        #5 ;
    end
end

reg    clk ;
reg    data_in, data_temp ;
initial begin
    forever @(posedge clk)      data_temp = data_in ;
end